Poulson incorporates a number of advances in its record-breaking 3.1B (yes, billion) transistors. It's socket-compatible with the older Tukwila processors and offers up to eight cores and 54MB of on-die memory. It's assumed that Intel will eventually offer Poulson products with less than eight cores and/or with lower amounts of available cache, but the company has announced no details on pricing or SKU structure.
Like Tukwila, Poulson shares a common platform with current Xeon 7500 products. Intel claims that the new chip delivers improved RAS (Reliability, Availability, Stability) services as compared to its predecessors and that it draws significantly less power than Tukwila would if the latter had been shrunk to a 32nm process.
The one thing Intel isn't discussing is what sort of performance boost Poulson can deliver relative to Tukwila. One of Poulson's most notable features is its doubled execution width. Up until now, all Itanium processors could only issue up to six instructions per clock cycle; Poulson boosts that to 12. In theory, Poulson's IPC (instructions per clock cycle) rate should be much higher than that of Tukwila when measured clock-for-clock.
Like all Itanium processors, however, Poulson relies much more heavily on the compiler's ability to schedule instructions for optimum execution than a standard x86 processor. The degree of performance improvement over previous processors, therefore, will depend on whether or not the compiler can hand over enough parallelized threads to take advantage of the architecture's increased capabilities.
Even with this caveat, Poulson should offer both an increase in absolute performance and in performance-per-watt when compared to previous Itanium processors. Longer term we might even see Itanium edging slightly beyond its current niche market status. Itanium's raw performance has never been in doubt when compared to conventional x86 processors using properly optimized code. Given sufficiently intelligent compilers, Itanium could begin to make economic sense in fields that couldn't previously justify the high cost of optimizing for the chip.