IDF: Inside Nehalem

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QuickPath, L3 cache, & Hyper-Threading

With the memory controller removed from the Northbridge chip, this also means no more front-side bus. Instead, Nehalem now uses a new interconnect that Intel calls "QuickPath." QuickPath is a point-to-point interconnect that Intel claims is much faster and more scalable than a front-side bus-based interconnect.

  

Another change for Nehalem is that it has three levels of cache--as opposed to the two levels of cache we're used to seeing on Intel's consumer-level Intel processors. There is a 64K L1 cache (32K Instruction, 32K Data), a 512K "mid-level" L2 cache (256K Data, 256K Instructions), and the shared L3 cache thats size will depend on the particular version of the processor. Intel is taking a modular approach with Nehalem's design, so it will be easier to manufacturer different versions of the chip with different features and L3 cache sizes. (The slide below titled "Core Designed for Performance" does not show the L3 cache.)

  

  

Nehalem also brings Hyper-Threading back to Intel processors. We haven't seen Hyper-Threading since the good old Pentium 4 days, save for Atom. While Hyper-Threading has in the past been criticized as being energy inefficient, Intel says the current iteration of Hyper-Threading is much more energy efficient. With Hyper-Threading, a processor with four physical cores appears to a system to have eight logical cores. Intel says it is also bringing Hyper-Threading to its Larrabee architecture.
 
Tags:  Nehalem, HAL, IDF, id

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