IDF: Inside Nehalem
This article represents the culmination of several IDF presentations, privates meetings, and conversations with Intel representatives from this past week--most of the slides are from a presentation give by Rajesh Kumar, Intel Fellow and Director of Intel's Director, Circuit, & Low Power Technologies.
Intel claims that Nehalem represents the biggest platform architecture change to date. This might be true, but it is not a grounds-up, completely new architecture design. An Intel representative told us that Nehalem "shares a significant portion of the P6 gene pool"--it does not include many new instructions and has approximately the same sized pipeline as Penryn. Nehalem is built upon Penryn, but with significant architectural changes to improve performance and power efficiency. It includes more external ports and deeper buffers. Nehalem will be manufactured on a 45nm process and will be the basis for Intel's forthcoming platforms, including the desktop, server, and mobile spaces.
One of the biggest changes Intel made with Nehalem is integrating the memory controller directly into the processor (which up to now has been located in the Northbridge of Intel's chipsets). Nehalem supports native DDR3 SDRAM memory (3 channels per socket) and up to the three DIMMs per channel. This three-channel memory architecture is a radical departure from the dual-channel SDRAM memory architecture that has existed since 2003 with the introduction of Springdale. Intel claims up to a 3.4x increase in memory bandwidth from Pernryn. As DDR3 memory speeds get faster, Intel says we could potentially see up to a 6x increase in memory bandwidth. Intel also claims that memory latencies have improved by more than 40 percent.