As the release of AMD’s Barcelona (also known as K-10) approaches, more details are starting to emerge. DailyTech has a few interesting details that shed some light on how the upcoming CPUs should work in existing sockets, and how they will gain some new features by pairing them with new “+” sockets:
"Yesterday, AMD held a press presentation in Munich, Germany to update
journalists about its upcoming K10 processor. AMD's Giuseppe Amato,
Technical Director of Sales and Marketing EMEA, had a few minutes to
talk about the architecture at length.
The integrated memory controller (IMC) will get a few new features in
the K10 core. When utilizing multiple memory modules, along with proper
BIOS implementation and mainboard routing, the IMC can access memory in
64-bit channels (72-bit if you use ECC). This way it is possible to
read and write data simultaneously, or improve efficiency for irregular
access patterns which increasingly occur in a quad-core environment.
This feature is available on AM2+ and F+ boards; on "old" socket AM2
and F boards the usual 128-bit dual-channel mode is available."
The story also says that AMD is gearing up for 45nm parts in '08, and
we might expect them to have 6MB of L3 cache. The story doesn't detail
any potential changes to the L1 or L2 caches or mention
potential SSE4 support.