Cray, "30,000 AMD dual-core Opterons = Petaflop Supercomputing!"
Cray XT4 Supercomputer Debuts With Petascale Capability
Significant Backlog of Large Orders
System Built on Cray XT Infrastructure Represents a Milestone for Cray's Adaptive Supercomputing Vision...
SEATTLE, WA -- (MARKET WIRE) -- November 13, 2006 -- Cray Inc. (NASDAQ: CRAY) today announced the availability of its next-generation massively parallel processing (MPP) system, the Cray XT4TM supercomputer. The powerful new supercomputer, previously code-named "Hood," is designed to easily and efficiently scale to a peak performance of more than one petaflops (1,000 trillion floating-point operations per second). The Cray XT4 supercomputer debuts with several large system orders announced earlier this year from leading organizations, including the Oak Ridge National Laboratory (ORNL), the National Energy Research Scientific Computing Center (NERSC) and the Finnish IT Center for Science (CSC).
The new Cray XT4 system is designed for superior scalability, incorporating the latest generation of AMD OpteronTM processors matched with expanded local and interconnect bandwidth that provides the industry-leading system balance necessary to optimize application performance at scale. The system is equipped with AMD Opteron dual-core processors that can be easily upgraded to AMD's quad-core processing technology in the future to deliver balanced petaflops performance.
The Cray XT4 supercomputer uses up to 30,000 AMD Opteron dual-core processors running a highly scalable operating system and interfaced to the Cray SeaStar2TM interconnect chip to provide unsurpassed scalability and performance. Unlike typical cluster architectures, in which many microprocessors share one communications interface, each AMD Opteron processor in the Cray XT4 system is coupled with its own interconnect chip. Providing six links in three dimensions, the unique Cray SeaStar2 chip uses its embedded routing capability to take advantage of HyperTransportTM technology and significantly accelerate communications among the processors.
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