Flash Scaling Issues Could Torpedo Its Future
NAND Flash and SSDs have become the darling of enthusiasts in recent years, thanks to a potent combination of improved read/write performance, virtually no latency, and lower power consumption compared to hard drives. A new report from the University of California San Diego, however, casts doubt on the long-term scalability of the format. The International Technology Roadmap for Semiconductors (ITRS)' most recent report backs up such statements.
Flash's fundamental problem is that the same technological innovations that are improving performance, power consumption, and cutting costs are also biting into its durability. The problem is illustrated in the graph below. Note that the best results, in this case, are at the bottom of the graph. The higher the data points are on the y-axis, the greater the bit error rate (BER). This data isn't theoretical; the research team tested a total of 45 flash chips made by six different manufacturers.
The chart shows that flash reliability remained constant or improved as manufacturers shifted from 72nm to 50nm production; 50nm MLC was capable of matching the reliability of 72nm SLC. 40nm designs also held reliability constant; the first TLC design appears at this node. Below 40nm, durability takes a marked turn for the worse; TLC error rates at 22nm are very high.
Poor reliability isn't the only concern. As process technology shrinks and transistors become more dense, the latency associated with the read/write process increases. This occurs with all types of NAND (SLC, MLC, and TLC), but TLC will suffer the most dramatic impact. The chart below shows the associated performance hit. The team states that "With current trends, our SSDs could be up to 34x larger, but the latency will be 1.7x worse for reads and 2.6x worse for writes. This will reduce the write latency advantage that SSDs offer relative to disk from 8.3x (vs. a 7 ms disk access) to just 3.2x."
According to the ITRS' 2011 report, even that 34x capacity is a pipe dream. While the researchers in California assumed Flash could scale to 6.5nm on conventional CMOS, the ITRS sees Flash possibly hitting a wall within six years. "For NAND flash...This geometric limitation will severely challenge scaling far below 20 nm half-pitch. In addition, fringing-field effect and floating-gate interference, noise margin, and few-electron statistical fluctuation... all impose deep challenges."
The report goes on to detail a number of avenues that might extend Flash's roadmap, including the widespread adoption of 3D manufacturing technologies, the availability of alternative types of memory, and the tremendous difficulty of ensuring that whatever solutions are designed match or exceed current reliability requirements. 3D stacking will allow Flash to continue pushing densities, but even the ITRS' most optimistic projections don't show solutions for the variety of problems confronting long-term scaling. The group's comprehensive tables are too extensive to reproduce here, but by 2016, an increasing number of technologies are labeled in red and denoted as "Manufacturable Solutions are NOT known."
Flash's fundamental problem is that the same technological innovations that are improving performance, power consumption, and cutting costs are also biting into its durability. The problem is illustrated in the graph below. Note that the best results, in this case, are at the bottom of the graph. The higher the data points are on the y-axis, the greater the bit error rate (BER). This data isn't theoretical; the research team tested a total of 45 flash chips made by six different manufacturers.
The chart shows that flash reliability remained constant or improved as manufacturers shifted from 72nm to 50nm production; 50nm MLC was capable of matching the reliability of 72nm SLC. 40nm designs also held reliability constant; the first TLC design appears at this node. Below 40nm, durability takes a marked turn for the worse; TLC error rates at 22nm are very high.
Poor reliability isn't the only concern. As process technology shrinks and transistors become more dense, the latency associated with the read/write process increases. This occurs with all types of NAND (SLC, MLC, and TLC), but TLC will suffer the most dramatic impact. The chart below shows the associated performance hit. The team states that "With current trends, our SSDs could be up to 34x larger, but the latency will be 1.7x worse for reads and 2.6x worse for writes. This will reduce the write latency advantage that SSDs offer relative to disk from 8.3x (vs. a 7 ms disk access) to just 3.2x."
According to the ITRS' 2011 report, even that 34x capacity is a pipe dream. While the researchers in California assumed Flash could scale to 6.5nm on conventional CMOS, the ITRS sees Flash possibly hitting a wall within six years. "For NAND flash...This geometric limitation will severely challenge scaling far below 20 nm half-pitch. In addition, fringing-field effect and floating-gate interference, noise margin, and few-electron statistical fluctuation... all impose deep challenges."
The report goes on to detail a number of avenues that might extend Flash's roadmap, including the widespread adoption of 3D manufacturing technologies, the availability of alternative types of memory, and the tremendous difficulty of ensuring that whatever solutions are designed match or exceed current reliability requirements. 3D stacking will allow Flash to continue pushing densities, but even the ITRS' most optimistic projections don't show solutions for the variety of problems confronting long-term scaling. The group's comprehensive tables are too extensive to reproduce here, but by 2016, an increasing number of technologies are labeled in red and denoted as "Manufacturable Solutions are NOT known."
