Intel offered dozens of technical seminars this past week and they all
touched on power efficiency to one degree or another. Intel has proposed power efficiency improvements to the memory bus, CPU-PCH linkages, SATA, wireless radios, displays, and much more.
Part of that rethinking process is focusing on seemingly settled interfaces and how they function. PCI-Express optimizations and the general shape of Intel's power optimization framework are shown below.
Here's Intel's next-generation platform, Shark Bay.
LTR refers to Latency Tolerance Messaging, a way of informing the platform how much a device can idle without compromising responsiveness or capability. By 2013, Intel expects the majority of devices that hook into Shark Bay to support some type of additional low-power operation. Long-term, the company's goal is to turn as many of these blocks green as it can.