More AMD G3MX Details Emerge

More AMD G3MX Details Emerge

A few weeks ago, news broke of an upcoming AMD technology co-developed with a couple of their IC partners dubbed G3MX, or the Socket G3 Memory eXtension.  In essence, G3MX is designed to be AMD’s answer to the current FB-DIMM (Fully Buffered) memory used on Intel’s high-end server and workstation platforms.  While DDR2 FB-DIMMs, that are outfitted with an AMB (Advanced Memory Buffer), offer a number of key benefits, including a serial point-to-point memory interface, improved reliability, scalability, signal integrity, increased bandwidth in some configurations, and higher capacity per memory channel, these benefits come at the cost of power consumption.

Due to the fact that each FB-DIMM has an on-board AMB, and the AMB chip is relatively power hungry, as you load up a system with more and more FB-DIMMs, power consumption can increase dramatically.  Because of the more complex nature of the FB-DIMMs themselves, they’re also more expensive than standard registered or un-buffered DIMMs.

While details regarding G3MX are sparse at the moment, the press release from last month gives a few details and somewhat explains the direction AMD is headed with future Opteron platforms.  We have, however, unearthed a few more specifics regarding G3MX that we thought you’d be interested in.

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The “future Opteron Platform” AMD mentions in their press releases seems to be based on a CPU currently codenamed “Hydra”, as you can see in the image above.  The processors will still feature an on-die memory controller, but unlike current platforms it will be geared for DDR3 memory.  The processors will interface with one or more G3MX chips, which in turn are connected to the memory ports.  G3MX will act as a memory port extender for the memory controller in the CPU socket and provides a serial link to the RAM.  Also, the electrical signaling between the memory controller and G3MX is based on HyperTransport 3.0.

The link between the memory controller and each G3MX chip is asymmetrical to allow for predominantly read transactions.  We should also note that the CPU G3MX link is 4x the speed of the memory data rate (4:1 ratio [high speed link : DRAM data rate]).  And to minimize power consumption, the G3MX chip will feature differential termination and likely be manufactured using an advanced process.

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Based on the information we’ve obtained, there will be up to four G3MX channels available to each Hydra CPU, suggesting that Hydra is a native quad-core variant.  In all likelihood, Hydra will also be MP capable.  G3MX can also interface with both registered and unbuffered DIMMs, which is where another of its benefits lies.  Because the G3MX chip will reside on the motherboard (or a daughterboard), systems using the technology can be outfitted with less expensive, standard DIMMs.  G3MX will also support higher speeds than current platforms and will likely have official DDR3-1600 support.  What G3MX should deliver is a means to relatively inexpensively populate a server or workstation with large amounts of high-speed RAM, without suffering from the signal integrity issues that plague current parallel memory interfaces when they’re heavily loaded.

G3MX chips are scheduled to tape out at the end of this year and sampling is supposed to begin in the first quarter of ’08.  If all goes according to plan, full production will begin in the fourth quarter of ’08 and platforms equipped with G3MX should arrive in the 2009 timeframe.

We have also received some information that Intel is headed in a similar direction with their future platforms.  We’ve heard that Intel is designing an “AMB2”, which like G3MX, is a “BOB” (buffer on board) type implementation, rather than being resident on DIMM modules. We’re not clear on the timeline for AMB2 and whether it will be a discrete chip or an integral block of a future Intel core logic chipset, but we do know it is coming.

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