JEDEC Lays Out DDR4 Memory Standard For Next-Gen Speedsters

JEDEC Lays Out DDR4 Memory Standard For Next-Gen Speedsters

Is the world okay as-is with just DDR2 and DDR3 memory? Perhaps. We could get by, yes, but what about pushing the envelope? What about faster, faster, faster? Well, it's about time for memory to take the next major leap in speed. JEDEC, a known name in the development of standards for the microelectronics industry, today announced the initial publication of its widely-anticipated Synchronous DDR4 (Double Data Rate 4) standard. That's DDR4, for those keeping count, which will offer "a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products." To facilitate comprehension and early adoption of the DDR4 standard, JEDEC is hosting a two-day DDR4 Technical Workshop in Santa Clara, CA on October 30 and 31, but it's probably the raw specs that you're interested in hearing about. Per JEDEC:

"The per-pin data rate for DDR4 is specified as 1.6 giga transfers per second to an initial maximum objective of 3.2 giga transfers per second. With DDR3 exceeding its original targeted performance of 1.6 GT/s, it is likely that higher performance speed grades will be added in a future DDR4 update. Other DDR4 attributes tightly intertwined with the planned speed grades, enabling device functionality as well as application adoption, include: a pseudo open drain interface on the DQ bus, a geardown mode for 2,667 MT/s per DQ and beyond, bank group architecture, internally generated VrefDQ and improved training modes.


The DDR4 architecture is an 8n prefetch with two or four selectable bank groups. This design will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each unique bank group. This concept will also improve overall memory efficiency and bandwidth, especially when small memory granularities are used. More information about additional features may be found on the JEDEC website. In addition, DDR4 has been designed in such a way that stacked memory devices may prove to be a key factor during the lifetime of the technology, with stacks of up to 8 memory devices presenting only a single signal load."

The publishing of this standard marks a very real milestone. At this point, the days of DDR3 are probably numbered, but it'll be a few months still before we hear about any real traction from OEMs implementing this in. Still, we can't wait to benchmark the new generation of memory modules. Bring on the speed!




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