IBM Launches OCtal-Core POWER7; Releases Benchmark Results
The x86 architecture has increasingly dominated the server market over the past decade but there's still a market for mainframe, big-iron servers. At present, Intel has challenged old guards Sun and IBM with a mixture of Nehalem-based Xeons and Itanium processors with the octal-core Nehalem-EX waiting in the wings. IBM isn't waiting for Nehalem-EX or Intel's new Itanium processor to hit the market before taking action of its own; Big Blue launched its POWER7 architecture on Monday. At 567mm2 and 32MB of on-die L3 cache, the new CPU is something of a beast.
Each POWER7 chip is divided into eight cores each with its own L2 cache. Each core is capable of handling four threads for a total of 32 threads in flight at any given time. The CPU is kept pumped full of data by 1-2 memory controllers (depending on the chip), with each controller capable of handling four channels of DDR3-1066. That's a total of 100GB/s of what IBM claims is sustained memory bandwidth. The chip is designed to scale up to 32 sockets, for a total of 256 processors and 1,024 threads in flight simultaneously. One of the most unique features of POWER7 is the CPU's enormous L3 cache. Rather than using conventional SRAM for its L3, IBM opted to build it out of eDRAM. This allowed the company to design a much larger cache with a lower transistor count than it otherwise could have. As we previously noted, IBM's POWER7 has 1.2B transistors, is 567mm2, and has 32MB of L3. By comparison, Intel's two billion transistor Tukwila (launched two days ago) is comparatively stodgy. At present, the only Tukwila listed on Intel's website is the 65nm Itanium 9330, a quad-core/eight-thread processor at 1.46GHz. It's unclear how much cache Tukwila actually has; reports around the web specify 30MB, but Intel's product sheet on the 9330 currently lists 20MB of cache.
POWER7 also compares favorably with the upcoming Nehalem-EX as far as transistor count and die complexity are concerned. There's no questioning the formidability of an octal-core Nehalem, but the CPU packs a whopping 2.3 billion transistors, 24 MB of cache, and die size that could be as large as 700mm2. We won't know exactly how these three architectures stack up against each other until more data is available, but POWER7 clearly packs a punch. Whether or not it's good enough to grab market share from either Itanium or the ever-present threat of x86 encroachment, however, remains to be seen. SPARC, for the record, is still technically in the fight; the company is planning a 16-core/128-thread Niagra processor built on 40nm bulk silicon. Given the company's steady loss of market share and the recent Oracle acquisition, however, it's not clear if Sun will continue to be a player in this market.
IBM has released SPEC benchmark data for certain POWER7 configurations; it's available here.
Each POWER7 chip is divided into eight cores each with its own L2 cache. Each core is capable of handling four threads for a total of 32 threads in flight at any given time. The CPU is kept pumped full of data by 1-2 memory controllers (depending on the chip), with each controller capable of handling four channels of DDR3-1066. That's a total of 100GB/s of what IBM claims is sustained memory bandwidth. The chip is designed to scale up to 32 sockets, for a total of 256 processors and 1,024 threads in flight simultaneously. One of the most unique features of POWER7 is the CPU's enormous L3 cache. Rather than using conventional SRAM for its L3, IBM opted to build it out of eDRAM. This allowed the company to design a much larger cache with a lower transistor count than it otherwise could have. As we previously noted, IBM's POWER7 has 1.2B transistors, is 567mm2, and has 32MB of L3. By comparison, Intel's two billion transistor Tukwila (launched two days ago) is comparatively stodgy. At present, the only Tukwila listed on Intel's website is the 65nm Itanium 9330, a quad-core/eight-thread processor at 1.46GHz. It's unclear how much cache Tukwila actually has; reports around the web specify 30MB, but Intel's product sheet on the 9330 currently lists 20MB of cache.
POWER7 also compares favorably with the upcoming Nehalem-EX as far as transistor count and die complexity are concerned. There's no questioning the formidability of an octal-core Nehalem, but the CPU packs a whopping 2.3 billion transistors, 24 MB of cache, and die size that could be as large as 700mm2. We won't know exactly how these three architectures stack up against each other until more data is available, but POWER7 clearly packs a punch. Whether or not it's good enough to grab market share from either Itanium or the ever-present threat of x86 encroachment, however, remains to be seen. SPARC, for the record, is still technically in the fight; the company is planning a 16-core/128-thread Niagra processor built on 40nm bulk silicon. Given the company's steady loss of market share and the recent Oracle acquisition, however, it's not clear if Sun will continue to be a player in this market.
IBM has released SPEC benchmark data for certain POWER7 configurations; it's available here.
