Leading Silicon-on-Insulator (SOI) wafer manufacturer Soitec published an updated roadmap today, detailing how it plans to make fully-depleted SOI technology (FD-SOI
) available through the 14nm process node, but there's some question as to the degree of industry support for the company's technology. In theory, FD-SOI could solve some of the scaling problems semiconductor foundries are facing, but the associated cost and difficulty of implementation are still unknowns.
"Each new generation of technology faces unique challenges, and we currently are at an inflection point where we cannot rely solely on traditional CMOS technology to solve them," said Handel Jones, founder and CEO of International Business Strategies. "If you look at the industry's technology migration path, you can see that everyone has fully depleted in their respective roadmaps. What Soitec is offering is a very attractive solution giving chip makers the means to reduce power consumption, increase performance, and provide lower cost solutions."
AMD has used SOI technology in all of its microprocessors since the launch of K8 back in 2003. That specific implementation of SOI is now known as PD-SOI (the PD stands for partially-depleted). The diagram below explains the difference, but the basics are fairly simple -- FD-SOI is a more advanced approach that eliminates what's known as the floating-body effect.
Unfortunately, FD-SOI is significantly more expensive than either PD-SOI or conventional bulk silicon. Intel highlighted this fact last year, when it unveiled its own Tri-Gate architecture, claiming that the increased cost of FD-SOI is why the company ultimately opted to go with its 3D transistor (FinFET) technology.
Soitec acknowledges the current cost-additive impact of FD-SOI, but when we spoke to the company, it pointed to its recent wins with STMicroelectronics as evidence that the industry wants FD-SOI-based hardware. We were assured that other company's have signed on as well, even if we can't disclose who they are yet. It also believes that future innovations will reduce the cost difference, partly thanks to an inherently simpler transistor layout compared to bulk silicon (provided other manufacturing issues can be brought under control).
The two new pieces of information announced today are the company's 3D transistor roadmap that combines FinFET and SOI at the 14nm node as well as the company's stated plans to deploy 28nm FD-SOI technology. This last item points to the difficulty foundries are having transitioning to new process nodes -- in the past, all new technologies were naturally folded into new nodes as the latter came online. Building FD-SOI at 28nm is a sign of how difficult it's become for the industry to collectively move to new nodes, and the dubious benefits of doing so.
Soitec wasn't willing to comment directly on what will happen if AMD stops using SOI, as seems increasingly likely given the company's refusal to divulge its future plans for either TSMC or GlobalFoundries. The company insists that demand for its products remains healthy and that this will continue. The lack of disclosure on all sides leaves us believing that the fabs themselves may still be weighing the potential benefits of various technologies.