Intel Signals Twilight Of Moore’s Law And The End Of Their Tick-Tock Process Cadence
For nearly a decade, Intel has followed a "tick-tock" release strategy for its processors. However, as Intel attempts to transition its manufacturing process from 14 nanometers to 10 nanometers, it's running into challenges that has the Santa Clara chip maker seemingly thinking about abandoning its tick-tock model.
Before we go any further, let's talk about the tick-tock model for a moment. Starting in 2007, Intel followed a cadence that consisted of transitioning existing architectures to a new process node (tick) followed by releasing a new architecture on that same node (tock). For example, Broadwell was a tick, as it was a 14nm die shrink of Haswell (22nm), whereas today's Skylake architecture is a tock, as it's a new 14nm architecture.
That cadence is about to be busted with the forthcoming release of Kaby Lake, another tock that will fill the gap left behind by Cannonlake's delay to late 2017. So instead of the usual tick-tock cycle, Intel will end up with a tock-tock-tick (Skylake, Kaby Lake, Cannonlake) release schedule, marking the first disruption in the tick-tock era.
Up to this point, it was thought this might be a one-time thing, However, Intel seems to suggest in its 10K filing that this will be the norm going forward. It even includes a graphic showing the old release schedule compared to what it's doing today.
"As part of our R&D efforts, we plan to introduce a new Intel Core microarchitecture for desktops, notebooks (including Ultrabook devices and 2-in-1 systems), and Intel Xeon processors on a regular cadence. We expect to lengthen the amount of time we will utilize our 14nm and our next-generation 10nm process technologies, further optimizing our products and process technologies while meeting the yearly market cadence for product introductions," Intel states in its filing.
There are two ways to read that. One is that Intel is merely stating what we already know, which is that Kaby Lake will disrupt the tick-tock cycle. The other way to read it is that the tick-tock schedule is yesterday's news, as evidenced by the accompanying graphic, and going forward Intel will follow a new release schedule.
Either way, this underscores the challenge of continuing to follow Moore's Law, which as revised in 1975 states that the number of transistors in a dense integrated circuit will double every two years. Intel has been able to achieve that for decades, but semiconductor process technology might be at a point where it's no longer feasible or practical for that matter.
Before we go any further, let's talk about the tick-tock model for a moment. Starting in 2007, Intel followed a cadence that consisted of transitioning existing architectures to a new process node (tick) followed by releasing a new architecture on that same node (tock). For example, Broadwell was a tick, as it was a 14nm die shrink of Haswell (22nm), whereas today's Skylake architecture is a tock, as it's a new 14nm architecture.
That cadence is about to be busted with the forthcoming release of Kaby Lake, another tock that will fill the gap left behind by Cannonlake's delay to late 2017. So instead of the usual tick-tock cycle, Intel will end up with a tock-tock-tick (Skylake, Kaby Lake, Cannonlake) release schedule, marking the first disruption in the tick-tock era.
Up to this point, it was thought this might be a one-time thing, However, Intel seems to suggest in its 10K filing that this will be the norm going forward. It even includes a graphic showing the old release schedule compared to what it's doing today.
"As part of our R&D efforts, we plan to introduce a new Intel Core microarchitecture for desktops, notebooks (including Ultrabook devices and 2-in-1 systems), and Intel Xeon processors on a regular cadence. We expect to lengthen the amount of time we will utilize our 14nm and our next-generation 10nm process technologies, further optimizing our products and process technologies while meeting the yearly market cadence for product introductions," Intel states in its filing.
There are two ways to read that. One is that Intel is merely stating what we already know, which is that Kaby Lake will disrupt the tick-tock cycle. The other way to read it is that the tick-tock schedule is yesterday's news, as evidenced by the accompanying graphic, and going forward Intel will follow a new release schedule.
Either way, this underscores the challenge of continuing to follow Moore's Law, which as revised in 1975 states that the number of transistors in a dense integrated circuit will double every two years. Intel has been able to achieve that for decades, but semiconductor process technology might be at a point where it's no longer feasible or practical for that matter.
